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SONY CMOS Image Sensors Overview - CONSUMER
CMOS Image Sensors for Consumer Applications
Medium format has traditionally referred to a film format in still photography and the related cameras and equipment that use film. In digital photography, medium format refers either to cameras adapted from medium-format film photography uses, or to cameras making use of sensors larger than that of a 35 mm film frame.
Sony have released Type 3.4 (44x33mm ) and Type 4.2 (53x40mm) image sensors with 100M pixels or 150M pixels.
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SONY Technology Guide
DOL-HDR: Digital Overlap High Dynamic Range
The HDR imaging function is one of the effective methods to improve picture quality.
In the DOL-HDR technology, an image processing technology for subjects with high contrast. It synthesizes different exposure conditions into an image so that both bright and dark data can be seen at the same time.
Therefore, it outputs brilliant colors are captured even when pictures are taken against bright light for both video imaging and still imaging.
SLVS-EC: Scalable Low Voltage Signaling Embedded Clock
SLVS-EC Rx IP provides SLVS-EC interface for Altera FPGA to receive image sensor data. SLVS-EC is Sony’s upcoming high-speed interface for next-generation high-resolution CMOS image sensors. This standard is tolerant of lane-to-lane skew because of embedded clock technology, so that it makes a board level design very easy in terms of high-speed and long distance transmission. Please see also our SLVS-EC IP Core solutions from Macnica.
Back-illuminated and stacked structure provide advanced functionality
Stacked CMOS Image Sensor is a Sony's CMOS image sensor that adopts a unique 'stacked structure.' This structure layers the pixel section, containing formations of back-illuminated pixels over the chip affixed with mounted circuits for signal processing, in place of conventional supporting substrates used for back-illuminated CMOS image sensors.
Conventional CMOS image sensors mount the pixel section and analog logic circuit on top of the same chip, which require numerous constraints when wishing to mount the large-scale circuits such as measures to counter the circuit scale and chip size, measures to suppress noise caused by the layout of the pixel and circuit sections, and optimizing the characteristics of pixels and circuit transistors.
Sony has succeeded in establishing a structure that layers the pixel section containing formations of back-illuminated structure pixels over the chip affixed with mounted circuits for signal processing, which is in place of supporting substrates used for conventional back-illuminated CMOS image sensors. By this stacked structure, large-scale circuits can now be mounted keeping small chip size. Furthermore, as the pixel section and circuit section are formed as independent chips, a manufacturing process can be adopted, enabling the pixel section to be specialized for higher image quality while the circuit section can be specialized for higher functionality, thus simultaneously achieving higher image quality, superior functionality and a more compact size. In addition, faster signal processing and lower power consumption can also be achieved through the use of leading process for the chip containing the circuits.
Back-illuminated structure provides higher sensitivity
Sony's back-illuminated CMOS image sensor improves sensitivity and noise reduction - the key factors to enhancing image quality, while radically realigning their fundamental pixel structure from front-illumination to back-illumination. It has retained the advantages of CMOS image sensors such as low power consumption and high-speed operation
With a conventional front-illumination structure, the metal wiring and transistors on the surface of the silicon substrate that form the sensor's light-sensitive area (photo-diode) impede photon gathering carried out by the on-chip lens, and this has also been an important issue in the miniaturization of pixels and widening optical angle response.
A back-illuminated structure minimizes the degradation of sensitivity to optical angle response, while also increasing the amount of light that enters each pixel due to the lack of obstacles such as metal wiring and transistors that have been moved to the reverse of the silicon substrate.
However, compared to conventional front-illuminated structures, back-illuminated structures commonly causes problems such as noise, dark current, defective pixels and color mixture that lead to image degradation and also cause a decrease in the signal-to-noise ratio.
To overcome this Sony has newly developed a unique photo-diode structure and on-chip lens optimized for back-illuminated structures, that achieves a higher sensitivity and a lower random noise without light by reducing noise, dark current and defect pixels compared to the conventional front-illuminated structure. Additionally, Sony's advanced technologies such as high-precision alignment have addressed any color mixture problems.
Higher Speed with Column-parallel A/D Conversion and Reducing Noise
The key to increased speed of Sony's CMOS Image Sensor can be found in parallel signal processing. CMOS sensors have analog-digital (A/D) conversion circuits that convert analog pixel signals into digital signals (Figure 1). Speed is increased by arranging thousands of these circuits in a horizontal array and allowing them to operate simultaneously. The A/D conversion circuits used in Sony's CMOS sensors have important characteristics, including the reduced size of the analog circuits in which noise is created, and automatic noise cancellation. This circuit design enables noise reduction to be combined with enhanced speed.